// a 16bit
// b 8bit
//c = a/b

module top(
           input wire [15: 0] a,
           input wire [7: 0] b,
           output wire [15: 0] result,
           output wire [15: 0] odd
       );

reg [15: 0] a_reg;
reg [7: 0] b_reg;
reg [31: 0] temp_a;
reg [31: 0] temp_b;
integer i;

always@( * )
	begin
		a_reg = a;
		b_reg = b;
	end

always@( * )
	begin
		temp_a = {16'h0, a_reg};
		temp_b = {b_reg, 16'h0};

		for (i = 0; i < 16;i = i + 1)
			begin
				temp_a = temp_a << 1;
				if (temp_a >= temp_b)
					begin
                        //加1等于加在了商上
						temp_a = temp_a - temp_b + 1;
					end
				else
					begin
						temp_a = temp_a;
					end
			end
	end


assign odd = temp_a[31: 16];
assign result = temp_a[15: 0];
endmodule
